Microprocessor chips fabricated with current CMOS technology are designed with great care to comprehend the circuit performance variations that occur as the process shifts from one tolerance extreme to the other. Designers have become accustomed to speak of MOS transistors having maximum drive capability as strong transistors and MOS transistors with minimum drive capability as weak transistors. At both of these extremes, the transistors are within specified process tolerance limits. It is desirable to maximize the useable yield of all functional devices even though different speed performance devices will be produced. Normally the whole performance distribution is salable.
In practice, designs are analyzed according to (a) transistor strength, (b) power supply voltage tolerances, (c) interconnect resistance and capacitance, and (d) operating temperature, among other possible parameters. Logic portions of the circuit must match as closely as possible the memory portions of the circuit and the interface should be optimized on every die as much as practical.
Experience has shown that to optimize overall yield, both memory designs and logic designs should carried out for highest possible speed performance considering all the design parameters. The most effective matching between elements of the logic and elements of memory has been shown to be achievable by adjusting memory performance downward incrementally as necessary to improve to usability of the full performance spread of the logic circuit portions. Hence, memory designers have conventionally designed-in memory trimming circuitry to incrementally lower the speed of the memory function. These memory trimming circuits are generally used to adjust the propagation delays in the read and write control circuits and have in some cases also been applied to adjustment of memory sense amplifier reference elements.
Pervious Techniques for Memory Trimming
Originally, memory trimming was achieved by utilizing spare gates by way of a revision of the chip interconnect pattern. This incurs significant costs and cycle times to produce revised photomask reticles and to complete fabrication of the revised product.
A later technique introduced to make memory trimming more practical laser fuses. Laser fuses built into the die may be blown to achieve many of the desired memory trimming adjustments. However, laser fuses must be large in chip area to ensure dependable laser beam hits.
Electrical Fuses for Programming
Electrical fuses (eFuses) are extremely attractive for this kind of application and have made a great impact on digital processor devices. Originally eFuses were applied to the obvious need for device programmability. The possibility of programming a device to do a specific task efficiently has made modest cost special purpose processors a reality. Many fusible interconnect links are constructed of materials such as deposited amorphous polysilicon.
These electrical fuses (eFuses) in VLSI silicon devices are programmed conventionally by applying a relatively large amount of power to the fuse body to melt and separate the fuse body material. This changes the eFuse resistance from a low pre-blow resistance to a high post-blow resistance. This result can be sensed to determine the state of the eFuse: unblown or blown.